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Incorporating external netlists : 'other'-elements

   

In another chapter, hierarchization of schematics was described. There is another method to introduce hierarchy, namely the incorporation of external netlists.

   

This method is useful if you want to use netlists created not by yourself but by other people or companies (for example, opamp macromodels or power transistor device models).

Let us assume that you are doing a design which uses discrete operational amplifiers commercially available . If you want to simulate your design, you will want to use ready-to-use libraries which contain netlists and describe the behaviour of your opamp.

To insert these netlists into your SPICE3 netlist, you need to place an 'other'-element. This element has to be created by the SPICECAD user and looks like a symbol, but with different default color (see page [*] , other_color) . However, the 'other' element has at least one property, the 'model'-property. This property contains the name of the netlist file which has to be inserted into the simulation netlist during netlisting. Such an elements will appear like a subcircuit in your netlist:
X12 n1 n2 n3 f_adder
The subcircuit definition is in file 'f_adder.m' which looks as follows:

.SUBCKT f_adder 1 2 3
B0 3 0 v=v(1)+v(2)
.ENDS f_adder

  This behaviour describes the hierarchical netlisting mode.

  There is another mode, the flat netlisting mode.

In this mode, the subcircuit is expanded and incorporated into the simulation netlist once for every appearance of an 'other'-element. In this mode, variables and expressions may be used within the subcircuit definition which looks as follows.

This is an example for file f_adder.m :
V1 1 0 param1
I2 2 0 param2
R1 3 0 param2+param4
L1 3 0 param4*param1
C1 3 0 param2/param4
M1 1 2 3 4 modelfile w=20u l=name5
M2 1 2 3 4 modelfile1 l=20u w=name5
Q1 2 3 4 5 modelfile_bjt area


In the flat mode, only these elements are allowed which also appear in the example with exactly the same syntax. This means, no AC , SIN or PWL sources ,no resistor temperature coefficients, no NS, ND or AREA parameters.

For the node numbers, the following restrictions have to be obeyed:

a) 0 ist the ground-node, the global ground. b) Nodes 1..n are external nodes . They will be replaced by external node numbers during netlisting. There must not be gaps between 1..n, each nodenumber between 1 and n must appear in the netlist.

This convention is like
.SUBCKT f_adder 1 2 3 . . . n
in a SPICE3 subcircuit definition.

n must be smaller or equal 100.

c) Nodes n+1 .. m are internal nodes. There may be gaps between n+1 and m. The number of different internal nodes is 100.

d) Device names, property names and model file names must not be longer than 40 characters.


next up previous contents
Next: Creating 'other'- elements Up: Hierarchical design Previous: Rules for local and
Martin Maschmann
1999-10-10